Workers are, or soon will be, anticipating the use of improved computer processors (CPU chips) like the INTEL “Pentium” that present new capabilities to a computer system. For instance, one may now contemplate some aspects of upgrading a “486 system” board (wherein the INTEL 486 CPU chip is featured) by using it conjunctively with a “Pentium CPU” (by INTEL).
This will require proper interfacing, for instance, of the cache memory in the Pentium CPU to/from existing memory on a '486 system board. Such is functionally represented in FIG. 1 where the Pentium CPU 1 has its cache coupled to a 486 memory 3 via an appropriate interface 5. As workers know, from a cache view point, data bits in memory are arranged in imaginary “chunks” called “lines”. And, transfers to/from cache are characteristically done in “Burst” mode with each “Burst” transferring a “line”; e.g. presently one 486 “Line-burst” transfer consists of a chain of four successive “sublines”, each subline consisting of thirty-two (32) bits (or four bytes e.g. see FIG. 2 representation, with Pentium sublines being twice this size).
Any “line” on a 486-memory is accessed between 16-byte (10 hex) boundaries. By contrast, one Pentium “Line Burst” consists of four successive 64-bit sublines (see FIG. 2), each subline thus being double the size of a “486 subline”. A Pentium subline resides in memory starting at 32-byte (20 h) boundary. Thus, a line Burst transfer moves four sublines in a certain order (not the order in memory); for such a transfer the CPU gives only the address of the “access-subline”; the system will transfer this access-subline first, followed by the three associated sublines in a certain prescribed order—varying according to the identity of the access-subline.
Thus, each one-line Burst Transfer from/to a Pentium cache to 486 memory should be done in two stages (because the number of bits transferred is doubled); and this presents the need to calculate the memory address where the second transfer-stage begins, that is, in terms of the FIG. 2 representation, an initial '486 Burst will begin at point A and end at point B, with the system, as presently constituted, automatically giving the beginning memory-address at A (i.e. where the first 486 subline is stored).
But, with a “double-burst”, from the Pentium cache, a like “second stage” is called for, beginning at point B; thus, the address of the “third” Pentium subline must be derived (not automatically given) to initiate this second stage (at point B), to complete the Pentium burst. And, since the sublines in such a Burst are not simply in an incremental address-order, the system will need to “calculate the third subline address” for such a Pentium (or like 4×64 bit) Burst—something the interface (e.g. 5 in FIG. 1) should provide. To do this is a salient object of this case (e.g. to provide a simple method, or algorithm, for such a calculation).
To recapitulate, a '486 system board will normally transfer a line starting with the first subline at the accessed address given by the Pentium CPU; and, when the '486 system board completes its line burst transfer, the Pentium cache will have transferred only two sublines, or one-half its burst. To complete the Pentium line burst, the system board should perform a second like transfer, starting at the third Pentium subline address (or point B, FIG. 2). This address is not given by the CPU; so I propose a way of doing so, automatically, at the interface. That is, I here propose an algorithm to calculate the “third-subline-address” from the given “first-subline address”.
Thus, it is an object hereof to address at least some of the foregoing needs and to provide one or several of the foregoing, and other, solutions.